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Search Publications by: Kin (Charles) Cheung (Fed)

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Displaying 226 - 250 of 251

The Negative Bias Temperature Instability vs. High-Field Stress Paradigm

May 18, 2009
Author(s)
Jason P. Campbell, Kin P. Cheung, John S. Suehle, A Oates
A new and more accurate fast-IDVG measurement methodology is utilized to examine the transient degradation and recovery associated with the negative-bias temperature instability (NBTI). The results reveal that the anomalously large initial degradations

Random Telegraph Noise in Highly Scaled nMOSFETs

April 26, 2009
Author(s)
Jason P. Campbell, Jin Qin, Kin P. Cheung, Liangchun (. Yu, John S. Suehle, A Oates, Kuang Sheng
Recently 1/f and random telegraph noise (RTN) studies have been used to infer information about bulk dielectric defects' spatial and energetic distributions. These analyses rely on a noise framework which involves charge exchange between the inversion

Channel Hot-Carrier Effect of 4H-SiC MOSFET

March 2, 2009
Author(s)
Liangchun (. Yu, Kin P. Cheung, John S. Suehle, Jason P. Campbell, Kuang Sheng, Aivars Lelis, Sei-Hyung Ryu
SiC MOSFET, as power device, can be expected to operate with high drain and high gate voltages, possibly leading to hot-carrier effect. However, hot-carrier degradation in a SiC MOSFET is difficult to detect because the as fabricated devices contain high

The Origins of Random Telegraph Noise in Highly Scaled SiON nMOSFETs

October 17, 2008
Author(s)
Jason P. Campbell, Jin Qin, Kin P. Cheung, Liangchun (. Yu, John S. Suehle, A Oates, Kuang Sheng
Random telegraph noise (RTN) has recently become an important issue in advanced circuit performance. It has also recently been used as a tool for gate dielectric defect profiling. In this work, we show that the widely accepted model thought to govern RTN

The transient behavior of NBTI - A new prospective

October 17, 2008
Author(s)
Kin P. Cheung, Jason P. Campbell
The Negative-Bias-Temperature-Instability (NBTI) is currently one of the most serious reliability issues in advanced CMOS technology. Specifically, the fast recovery of NBTI degradation immediately after stress is removed has recently become a hot topic

Oxide Reliability of SiC MOS Devices

October 12, 2008
Author(s)
Liangchun (. Yu, Kin P. Cheung, Jason P. Campbell, John S. Suehle, Kuang Sheng
Silicon carbide possesses excellent material properties for high temperature, high frequency and high power applications. Among all the device structures, MOSFET has advantages such as low gate leakage current, easier device control etc., and therefore

An Accurate Capacitance-Voltage Measurement Method for Highly Leaky Devices

September 1, 2008
Author(s)
Yun Wang, Kin P. Cheung, Y.J. Choi, Byoung Hun Lee
Accurate CV measurement becomes extremely difficult in advanced CMOS technology due to high level of leakage across the gate dielectric. Recently, a new Time-Domain-Reflectometry (TDR) based CV measurement method was introduced. This new method offers ease

New Insight into NBTI Transient Behavior Observed from Fast-GM Measurements

September 1, 2008
Author(s)
Jason P. Campbell, Kin P. Cheung, John S. Suehle
Fast-IDVG measurements have become an increasingly important tool to examine MOSFET transient degradation. The threshold voltage (VTH) extracted from fast-IDVG measurements is often used to infer the transient behavior of trapped charged in the gate

Negative-Bias Temperature Instability Induced Electron Trapping

July 21, 2008
Author(s)
Jason P. Campbell, Kin P. Cheung, John S. Suehle, A Oates
Despite four decades of research, the physics responsible for the negative bias temperature instability (NBTI) in p-channel metal-oxide-silicon field-effect-transistors is still unresolved. The current NBTI debate focuses on the dominance of either a hole

Electron Trapping: An Unexpected Mechanism of NBTI and Its Implications

June 17, 2008
Author(s)
Jason P. Campbell, Kin P. Cheung, John S. Suehle, A Oates
We utilize fast-IdVg measurements to examine NBTI recovery over a time scale of 2usecs to 1000 seconds. The extracted DVTH and %GM degradation data clearly demonstrates the presence of hole as well as electron trapping and detrapping. The hole and electron

The Challenge of Measuring Defects in Nanoscale Dielectrics

May 26, 2008
Author(s)
Kin P. Cheung, John S. Suehle
Defects in nanoscale gate dielectric of MOS devices can exchange charges with the substrate via quantum mechanical tunneling. This characteristic has been utilized in many measurement methods to measure the defects and its spatial distribution. In some

STRESS-INDUCED DEFECT GENERATION IN HFO2/SIO2 STACKS OBSERVED BY USING CHARGE PUMPING AND LOW FREQUENCY NOISE MEASUREMENTS

April 30, 2008
Author(s)
Hao Xiong, Dawei Heh, Shuo Yang, Moshe Gurfinkel, Gennadi Bersuker, D. E. Ioannou, Curt A. Richter, Kin P. Cheung, John S. Suehle
A novel approach combining the low frequency drain current noise and the frequency-dependent charge pumping techniques has been employed to extract the trap densities in both the interfacial SiO2 layer and high-k layer in the n-type MOSFETs with HfO2/SiO2

THE FAST INITIAL THRESHOLD VOLTAGE SHIFT: NBTI OR HIGH-FIELD STRESS

April 27, 2008
Author(s)
Jason P. Campbell, Kin P. Cheung, John S. Suehle
Recent 'NBTI' studies have come to involve very high electric fields, yet these same studies are used to criticize the lower field 'NBTI' models. This study examines both high- and low-field degradation phenomena by monitoring the initial threshold voltage